The present invention relates to the manufacturing of semiconduct or devices, and more particularly, to copper and copper alloy metallization in semiconductor devices.
The escalating requirements for high density and performance associated with ultra large scale integration (ULSI) semiconductor device wiring are difficult to satisfy in terms of providing sub-micron-sized, low resistance-capacitance (RC) metallization patterns. This is particularly applicable when the sub-micron-features, such as vias, contact areas, lines, trenches, and other shaped openings or recesses have high aspect ratios (depth-to-width) due to miniaturization.
Conventional semiconductor devices typically comprise a semiconductor substrate, usually of doped monocrystalline silicon (Si), and a plurality of sequentially formed dielectric interlayer dielectrics and electrically conductive patterns. An integrated circuit is formed therefrom containing a plurality of patterns of conductive lines separated by inter wiring spacings, and a plurality of interconnect lines, such as bus lines, bit lines, word lines and logic interconnect lines. Typically, the conductive patterns of vertically spaced metallization layers are electrically interconnected by vertically oriented conductive plugs filling via holes formed in the interlayer dielectric layer separating the metallization layers, while other conductive plugs filling contact holes establish electrical contact with active device regions, such as a source/drain region of a transistor, formed in or on a semiconductor substrate. Conductive lines formed in trench-like openings typically extend substantially parallel to the semiconductor substrate. Semiconductor devices of such type according to current technology may comprise five or more levels of metallization to satisfy device geometry and micro miniaturization requirements.
A commonly employed method for forming conductive plugs for electrically interconnecting vertically spaced metallization layers is known as xe2x80x9cdamascenexe2x80x9d-type processing. Generally, this process involves forming an opening (or via) in the dielectric interlayer, which will subsequently separate the vertically spaced metallization layers. The via is typically formed using conventional lithographic and etching techniques. After the via is formed, the via is filled with a conductive material, such as tungsten (W), using conventional techniques. Excess conductive material on the surface of the dielectric interlayer is then typically removed by chemical mechanical planarization (CMP).
A variant of the above-described process, termed xe2x80x9cdual damascenexe2x80x9d processing, involves the formation of an opening having a lower contact (or via) hole section which communicates with an upper trench section. The opening is then filled with a conductive material to form a conductive plug that electrically contacts the lower metallization layer. As with the previous process, excess conductive material on the surface of the dielectric interlayer is then removed by CMP. An advantage of the dual damascene process is that the conductive plug and the upper metallization layer are formed simultaneously.
High performance microprocessor applications require rapid speed of semiconductor circuitry, and the integrated circuit speed varies inversely with the resistance and capacitance of the interconnection pattern. As integrated circuits become more complex and feature sizes and spacings become smaller, the integrated circuit speed becomes less dependent upon the transistor itself and more dependent upon the interconnection pattern. If the interconnection node is routed over a considerable distance, e.g., hundreds of microns or more, as in sub-micron technologies, the interconnection capacitance limits the circuit node capacitance loading and, hence, the circuit speed. As integration density increases and feature size decreases, in accordance with sub-micron design rules, the rejection rate due to integrated circuit speed delays significantly reduces manufacturing throughput and increases manufacturing costs.
One way to increase the circuit speed is to reduce the resistance of a conductive pattern. Conventional metallization patterns are typically formed by depositing a layer of conductive material, notably aluminum (Al) or an alloy thereof, and etching, or by damascene techniques. Al is conventionally employed because it is relatively inexpensive, exhibits low resistively and is relatively easy to etch. However, as the size of openings for vias/contacts and trenches is scaled down to the sub-micron range, step coverage problems result from the use of Al. Poor step coverage causes high current density and enhanced electromigration. Moreover, low dielectric constant polyamide materials, when employed as dielectric interlayers, create moisture/bias reliability problems when in contact with Al, and these problems have decreased the reliability of interconnections formed between various metallization layers.
One approach to improved interconnection paths in vias involves the use of completely filled plugs of a metal, such as W. Accordingly, many current semiconductor devices utilizing VLSI (very large scale integration) technology employ Al for the metallization layer and W plugs for interconnections between the different metallization levels. The use of W, however, is attendant with several disadvantages. For example, most W processes are complex and expensive. Furthermore, W has a high resistivity, which decreases circuit speed. Moreover, Joule heating may enhance electromigration of adjacent Al wiring. Still a further problem is that W plugs are susceptible to void formation, and the interface with the metallization layer usually results in high contact resistance.
Another attempted solution for the Al plug interconnect problem involves depositing Al using chemical vapor deposition (CVD) or physical vapor deposition (PVD) at elevated temperatures. The use of CVD for depositing Al is expensive, and hot PVD Al deposition requires very high process temperatures incompatible with manufacturing integrated circuitry.
Copper (Cu) and Cu-based alloys are particularly attractive for use in VLSI and ULSI semiconductor devices, which require multi-level metallization layers. Cu and Cu-based alloy metallization systems have very low resistivities, which are significantly lower than W and even lower than those of previously preferred systems utilizing Al and its alloys. Additionally, Cu has a higher resistance to electromigration. Furthermore, Cu and its alloys enjoy a considerable cost advantage over a number of other conductive materials, notably silver (Ag) and gold (Au). Also, in contrast to Al and refractory-type metals (e.g., titanium (Ti), tantalum (Ta) and (W), Cu and its alloys can be readily deposited at low temperatures formed by well-known xe2x80x9cwetxe2x80x9d plating techniques, such as electroless and electroplating techniques, at deposition rates fully compatible with the requirements of manufacturing throughput.
A problem that can be caused by the use of copper and copper-based alloys results from copper having a relatively large diffusion coefficient into dielectric materials, such as low k dielectric materials. Once copper is diffused into these materials, copper can cause the dielectric strength of these materials to decrease. Thus, if copper from a plug or metallization layer diffuses into the dielectric layer, the layer can become more conductive and the increase in conductivity can cause short circuits between adjacent conductive regions. These short circuits can therefore result in failure of the semiconductor device. For this reason, copper conductors are encapsulated by at least one diffusion barrier to prevent diffusion of the copper into the dielectric layer. However, the use of conventional barrier and adhesion layers within the opening, such as a TiN or TaN layer, may undesirably result in an increase in the contact resistance.
Even with the encapsulation of a copper conductor by a diffusion barrier layer, copper contamination of the dielectric layer can still result during the formation of an opening in the dielectric layer and etching of the diffusion barrier. As depicted in FIG. 4, which shows a prior art damascene opening, a copper material is provided in substrate layer (a metallization layer) 100. The interconnect structure includes a barrier diffusion layer 102 (such as silicon nitride), a dielectric layer 104 and a capping layer 106. During an initial etching step, an etchant is applied to etch through the cap layer 106 and the dielectric layer 104. The etching stops at the diffusion barrier 102. The complete opening 108 is formed by etching of the diffusion barrier 102. However, during the etching of the diffusion barrier 102 within the pattern opening 108, some of the copper from the underlying substrate 100 sputters up from the substrate layer 100 into the dielectric layer 104. The copper, represented as particles 110, enters through the sidewalls 112 of the opening 108.
Copper contamination can also occur as a result of the use of reverse physical sputtering to clean the first metallization layer 100 and to round the corners of trenches and vias. Reverse physical sputtering is a process by which atoms or molecules from the surface of a material are dislocated or removed by the impact energy of gas ions, which are accelerated in an electric field. This process involves the creation of a glow discharge or plasma between an anode and a cathode, such as a semiconductor device, wherein the current therebetween is composed of electron flow to the anode and positive ion flow to the cathode. The ions are created by the ionization of gas molecules, such as argon, existing within the flow discharge region between the anode and cathode. The ionization results from the collision of gas particles with the electron flow from the cathode to the anode. A focused beam of these ions can be directed to a very small point on a semiconductor device and then scanned, raster fashion, over a surface where material is to be removed. As an ion impinges on the semiconductor device surface, momentum is transferred from the ion to the impact surface resulting in the removal of one or more surface atoms.
There is a need for a method of forming a metal interconnect structure that substantially prevents copper contamination in the dielectric layer, caused by etching of the diffusion barrier or reverse sputtering to clean the first metallization layer, or similar processes, in which conductive material may be dislodged and diffused into a dielectric layer. Also, there is a need for a method of providing a barrier within an opening that provides adhesion for a seed layer, but has a low resistance.
These and other needs are met by embodiments of the present invention which provide a method of forming an interconnect structure comprising the steps of etching through a dielectric layer to a diffusion barrier to create an opening with a bottom and sidewalls, the etching stopping on the diffusion barrier. A nitride barrier layer is conformally deposited on the bottom and sidewalls of the opening. This is followed by conformally depositing a first metal layer on the nitride barrier layer. The nitride barrier layer and the first metal layer are directionally etched to remove the diffusion barrier, the nitride barrier layer and the first metal layer from the bottom of the opening, while maintaining the nitride barrier layer and the first metal layer on the sidewalls of the opening. The nitride barrier layer and the first metal layer substantially prevent scattering and diffusion of conductive material underlying the diffusion barrier into the dielectric layer. A second metal layer is conformally deposited in the opening, with a copper seed layer being electrolessly deposited over the second metal layer. Copper or a copper-based alloy is electroplated in the opening.
In certain embodiments of the present invention, the first and second metal is tantalum, and the second metal layer is between about 25 xc3x85 and about 100 xc3x85. The conformal deposition of the nitride barrier layer and the tantalum on the sidewalls of the opening acts as a passivation layer that prevents the conductive material, such as copper, from diffusing into the dielectric layer during the etching of the diffusion barrier or sputter cleaning of the conductive material. The thin second metal layer of tantalum provides a nucleation step for the electroless plating of the copper seed layer. At the same time, the thinness of the second metal layer creates only a very low contact resistance between the second metal layer and the underlying substrate. In certain embodiments, the nitride barrier layer and the first metal (e.g. tantalum) layer are deposited without air break. An air break is permissible between the deposition of the second metal layer and the electroless plating of the copper seed layer. The electroless deposition of the copper seed layer provides a conformal copper layer, which makes it easier to form a completely filled damascene structure during electroplating. Furthermore, electroless deposition of the copper seed layer provides good  less than 111 greater than  texture copper, in comparison to CVD copper deposited directly on the barrier material. The improvement in texture provides better electromigration characteristics.
By forming a conformal layer of barrier material on the sidewalls of the opening, and only then directionally etching the barrier Material to remove the diffusion barrier as well as the barrier material from the bottom of the opening, a sufficient amount of barrier material remains on the sidewalls to prevent the scattering and diffusion of the conductive material, such as copper, into the dielectric layer. This controllably prevents the detrimental effects of copper diffusion into the dielectric layer and potential failure of the semiconductor device. The two layers of metal on the sidewalls of the opening provide sufficient barrier protection for the dielectric material from the copper after the conductive feature is formed. However, since only a single layer of metal is on the bottom of the opening, the contact resistance is very low.
The earlier stated needs are also met by embodiments of the present invention which provide a metal interconnect structure comprising a substrate containing copper or copper-based alloy, a diffusion barrier layer on the substrate, a dielectric layer on the diffusion barrier layer, and an opening in the dielectric layer and diffusion barrier layer, this opening have sidewalls and a bottom that is formed by the substrate. A nitride layer is provided substantially only on the sidewalls. A first metal layer is substantially only on the nitride layer. A second metal layer is on the first metal layer and on the bottom of the opening. An electrolessly plated copper seed layer is on the second metal layer and electroplated copper, or a copper-based alloy, is on the copper seed layer.
The earlier stated needs are also met by embodiments of the present invention which provide a method of forming a copper interconnect structure comprising the steps of forming an opening in a low k dielectric layer, this opening being bounded by sidewalls of the dielectric layer and a diffusion barrier underlying the dielectric layer and forming a horizontal surface. Nitride and a first tantalum layer are conformally deposited within the opening such that the diffusion barrier is covered with a horizontal layers of nitride and tantalum and the sidewalls are covered with vertical layers of nitride and tantalum. Directional etching is performed to remove the horizontal layers of nitride and tantalum, as well as the diffusion barrier at the bottom of the opening. A second layer of tantalum is conformally deposited in the opening. A copper seed layer is electrolessly deposited on the second layer of tantalum. Copper or a copper-based alloy is electroplated in the opening.
The foregoing and other features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.